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Title Architectural aspects of design for low static power consumption
Author Hans, Martin
Supervisor Stassen, Flemming (Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2004
Abstract In the presence of non-negligible leakage power, the way to design architectures for low power consumption may have changed. This master's thesis represents one step towards exploring low power design again. This thesis shows, that area is not a sufficient predictor of leakage power consumption when delay requirements are tight. Architectural voltage scaling is re-evaluated and it is shown that it does not always reduce leakage power. Opportunities for reducing the leakage associated with repeaters used in long on-chip wires are explored. Furthermore, a novel architecture level power estimation method is presented which allows the designer to explore design space early in the design process.
Imprint Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU : DK-2800 Kgs. Lyngby, Denmark
Keywords leakage power; static power; total power; architecture; high level power estimation; architectural voltage scaling; repeater leakage
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Admin Creation date: 2006-06-22    Update date: 2012-12-21    Source: dtu    ID: 154756    Original MXD