Beta 1


Title Design of CMOS cell libraries for minimal leakage currents
Author Hansen, Jacob Gregers
Supervisor Stassen, Flemming (Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2004
Abstract Leakage due to scaling down CMOS device sizes will be the major power consumption source in cell based IC design in a few years. This work addresses the problem of this leakage, investigating the possibilities of utilizing alternative logic families instead of static CMOS for the creation of a low leakage cell library. For this purpose, MTCMOS, CPL and Domino logic are investigated for leakage characteristics and are found unusable for low leakage design. Using cell libraries of small logic cells for IC design is found to be the major reason for much of the leakage. Synthesizing without cell boundaries by building larger cells reduces the leakage problem greatly. A new synthesis flow and cell library is proposed.
Imprint Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU : DK-2800 Kgs. Lyngby, Denmark
Keywords Low leakage CMOS; CPL; Domino; MTCMOS; MacroCMOS; Synthesis for low leakage design.
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Admin Creation date: 2006-06-22    Update date: 2012-12-21    Source: dtu    ID: 154758    Original MXD