Beta 1


Title System Level Platform Modeling for System-on-Chip
Author Ritter, David
Supervisor Madsen, Jan (Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2004
Abstract SoC design using IP-based design methodologies allows a large degree of design flexibility. Designers may wish to use design space exploration techniques to find optimal SoC designs for a given application. To do so, however, fast and accurate estimation of each design s performance is needed. In this project, SoC performance estimation techniques are explored, focusing on processor-based platforms. A flexible methodology, the SoC Platform Architecture Model (SPAM), is developed for specifying platform configurations, component properties, and workload properties. A set of performance models for processors, bus interconnect, and shared or private memories is presented. These models are then combined using the SPAM methodology, and applied to modeling of a variety of single processor and multiprocessor SoC platforms. The potential for extension of the SPAM modeling system is also explored.
Imprint Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU : DK-2800 Kgs. Lyngby, Denmark
Fulltext
Original PDF imm3284.pdf (0.77 MB)
Admin Creation date: 2006-06-22    Update date: 2012-12-21    Source: dtu    ID: 154798    Original MXD