Beta 1


Title Simulation based sequential circuit automated test pattern generation
Author Yuan, Jing
Supervisor Stassen, Flemming (Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2004
Abstract The aim with this paper is to design a high e cient sequential ATPG on single stack-at fault model.A new approach for sequential circuit test generation is proposed in this paper.With combining the advantage of logic simulation based ATPG and fault simulation based ATPG, higher fault coverage and shorter test sequential length are achieved for benchmark circuit instead of pure logic or fault simulation based ATPG. A new high e cient fault simulation algorithm which is based on PROOFs [39 ]is presented. Here two new techniques are used to accelerate parallel fault simulation:1) X algorithm preprocessing, 2) Dynamic fault ordering method. Based on experiment result,these two heuristic accelerate fault simulation by 1.2 time in fault simulation. Two metaheuristic algorithms,genetic algorithm and Tabu search,are investigated in test generation process.These algorithms are used to generate population of candidate test vectors and optimize vectors.
Imprint Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU : DK-2800 Kgs. Lyngby, Denmark
Fulltext
Derived PDF imm3263.pdf (0.41 MB)
Original Postscript imm3263.ps (10.71 MB)
Admin Creation date: 2006-06-22    Update date: 2012-12-21    Source: dtu    ID: 154815    Original MXD