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Title High-Level Modeling of Network-on-Chip
Author Stuart, Matthias Bo (Computer Science and Engineering, Informatics and Mathematical Modelling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Stensgaard, Mikkel Bystrup (Computer Science and Engineering, Informatics and Mathematical Modelling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Supervisor Sparsø, Jens (Computer Science and Engineering, Informatics and Mathematical Modelling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2006
Abstract This report describes the design, implementation and testing of a high-level model of an asynchronous network-on-chip called MANGO that has been developed at IMM, DTU. The requirements to the model are twofold: It should be timing accurate, which allows it to be used in place of MANGO, and it should have a high simulation speed. For these purposes, different approaches to modeling network-on-chip and asynchronous circuits have been investigated. Simulation results indicate a simulation speedup on a magnitude of a factor 1000 over the current implementation of MANGO, which is implemented as netlists of standard cells.
Series IMM-Thesis-2006-83
Fulltext
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Admin Creation date: 2007-06-11    Update date: 2007-09-14    Source: dtu    ID: 200731    Original MXD