Beta 1

Title Modeling Of Arithmetic Units For Early Design Space Exploration Of Algorithms Trade-Offs
Author Zhang, Bing
Supervisor Nannarelli, Alberto (Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2008
Abstract This thesis work is part of a larger research project on developing a tool which would allow the exploration of arithmetic algorithms and designs in a standardized and flexible way. The tool should provide a good estimate of the performance, in terms of delay, area and power dissipation, of the implementation of a given algorithm at an early stage of the design process, and allow a standardized comparison with preexisting implementations. This thesis is focus on the delay and area estimation and comparison based on logical effort with given algorithms. In addition, basic modules such as adders, multipliers and dividers are developed and verified against actual implementation of standard arithmetic operators. It verified that logical effort can be used for different modules' delay estimation in this tool, taking into account a number of design constraints/specifications such as: bit-width, fan-out and optimization criteria. In the implementation part, several modules such as carry save adders (CSA), carry propagate adders (CPA), Radix 4 multiplier, Radix 2, 4 and 8 dividers are implemented with VHDL and estimated with software tools Spice and Synopsys. Standard blocks that can be used for future exploration are estimated, and nonstandard blocks are estimated separately.
Series IMM-M.Sc.-2008-21
Original PDF ep08_21.pdf (0.75 MB)
Admin Creation date: 2008-03-07    Update date: 2008-07-15    Source: dtu    ID: 211563    Original MXD