||FPGA Prototyping of Asynchronous Networks-on-Chip
||Lassen, Jon Neerup
||Sparsø, Jens (Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
||Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
||Network-on-chip (NoC) is an emerging paradigm for handling the communication in large system-on-chips. This project investigates the ability to prototype
asynchronous NoCs on FPGAs.
The implementation of asynchronous circuits on standard FPGAs is highly experimental, therefore the rst part of the project has been to establish a design
ow for the implementation of asynchronous circuits on FPGAs. In the project
an asynchronous best-effort NoC for an FPGA has been successfully developed.
The NoC implementation consists of a router and network adapters and is implemented using a 4-phase bundled data handshake protocol. Cores connects
to the network using an OCP interface. To demonstrate the NoC it has been
implemented in a small multi-processor prototype using a mesh topology for the
Creation date: 2008-03-26
Update date: 2008-07-15