Beta 1


Title FPGA Prototyping of Asynchronous Networks-on-Chip
Author Lassen, Jon Neerup
Supervisor Sparsø, Jens (Computer Science and Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2008
Abstract Network-on-chip (NoC) is an emerging paradigm for handling the communication in large system-on-chips. This project investigates the ability to prototype asynchronous NoCs on FPGAs. The implementation of asynchronous circuits on standard FPGAs is highly experimental, therefore the rst part of the project has been to establish a design ow for the implementation of asynchronous circuits on FPGAs. In the project an asynchronous best-effort NoC for an FPGA has been successfully developed. The NoC implementation consists of a router and network adapters and is implemented using a 4-phase bundled data handshake protocol. Cores connects to the network using an OCP interface. To demonstrate the NoC it has been implemented in a small multi-processor prototype using a mesh topology for the network.
Series IMM-M.Sc.-2008-26
Fulltext
Original PDF ep08_26.pdf (12.10 MB)
Admin Creation date: 2008-03-26    Update date: 2008-07-15    Source: dtu    ID: 211821    Original MXD