Beta 1

Title Design of a Low Power Division Unit for Hearing Aids
Author Winther-Almstrup, Rasmus
Supervisor Nannarelli, Alberto (System-on-Chip Hardware, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2008
Abstract Hearings aids have changed a lot over the last decade. From being entirely analog to the modern digital hearing aids, the need for specialised functions have increased. This is the motivation behind this thesis, to implement a low power division unit for hearing aids that can be used as a specialised function. The algorithm chosen is the digit-recurrence algorithm [4], because it is well documented and has a nice trade off between power and speed. Two radices are implemented, radix-4 and radix-8. We require that six bits are realised of the result each iteration and since radix-4 only realises two, while the radix-8 realises three, the architectures are unrolled to meet the requirement. For each architecture the impact on changing the adder representation is explored and we discover that mixed architectures with a carry-propagate adder and carry-save adders dissipates less power than architectures with only carry-save adders. The best architecture in terms of power proves to be the radix-4 architecture with a [4:2] carry-save and a carry-propagate adder. Since the division unit requires a specific data representation, and because w are using another data representation, a way to normalise the inputs is presented. The normalisation logic is shown to have another benefit since it allows the implementation of cycle prediction. The cycle prediction allows us to stall the division if it is done before the worst case running time. The combination of digit-recurrence and cycle prediction is new. With the implementation of cycle prediction the division is shown to be better in terms of power compared to the divider with the data representation it was designed for. Finally the impact of clock gating compared to registers with load enable is explored where clock gating is shown to be best. The final divider with low power optimisations and cycle prediction is shown to dissipate 24% less power than the standard digit-recurrence divider. The architectures is implemented in 90 nm technology running at 1.0V
Series IMM-M.Sc.-2008-32
Original PDF ep08_32_net.pdf (2.31 MB)
Admin Creation date: 2008-04-01    Update date: 2008-07-15    Source: dtu    ID: 213584    Original MXD