Beta 1

Title Softbit Detector / Equalizer for GSM release 7
Author Wu, Xia
Supervisor Nannarelli, Alberto (System-on-Chip Hardware, Informatics and Mathematical Modelling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2008
Abstract This thesis deals with the implementation of a power/area optimal equalizer according to the recently updated GSM specification. The equalizer should support GMSK, QPSK, 8PSK, 16QAM and 32QAM modulation types. For the high order modulation types, the traditional Maximum Likehood Sequence Estimation( MLSE) algorithm is not able to process the burst within the required time. Therefore two different algorithms with reduced computation complexity are studied in the thesis: the Reduced-State Sequence Estimation with Setpartitioning( RSSE) algorithm and the Sphere Decoding(SD) algorithm. The RSSE algorithm reduces the complexity by grouping the states into subsets in the trellis structure, while the SD algorithm addresses the problem by constraining the trellis search with a threshold. Since the two algorithms optimize the MLSE approach in different aspects, a hybrid algorithm (RSSE T) is proposed. The project implemented all three algorithms in RTL and compared their performance in area, power and delay. The SD algorithm is implemented in two different approaches, named SD I and SD II. The performance evaluation shows the area cost of the RSSE, the SD I, the SD II and the RSSE T equalizers is 62102 m2, 94050 m2, 182965 m2, and 78317m2 respectively, for the given 45nm CMOS technology. When clocked at 200MHz and given a normal operating voltage between 1.0-1.3V, the power consumption of the four equalizers is typically less than 8.2mW, 6.8mW, 10.3mW and 7.8mW, respectively. The SD I equalizer is unable to satisfy the timing requirements, thus is the least interesting candidate for physical implementation. The RSSE T equalizer consumes constantly 30% less power than the SD II equalizer, and in the best case reduces 50% of the power consumed by the RSSE equalizer, therefore it is the most efficient implementation among these four designs.
Series IMM-M.Sc.-2008-91
Original PDF ep08_91_net.pdf (1.55 MB)
Admin Creation date: 2008-09-26    Update date: 2010-10-28    Source: dtu    ID: 223864    Original MXD