||Design of a Hardware Network Address Translation Unit for a Single Chip High-Speed Ethernet Router
||Jensen, Martin Rolsted
||Sparsø, Jens (System-on-Chip Hardware, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
||Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
||The general objective of this thesis work is to design and evaluate a Network and
Address & Port Translation (NAPT) core, which is typically found in and as
a part of a Small- Office or Small-Home (SOHO) Ethernet router. The NAPT
core makes it possible for e.g. a wireless router to share only one public IP
address, provided by an Internet Service Provider (ISP), with several internal
hosts on a private Local Area Network (LAN), even though the internal hosts
are connecting simultaneously.
The main functionality of the NAPT core is to modify the header information
of both in- and outbound IP packets transversing the NAPT. This process of
manipulating, also called translation, involves time-critical lookups in various
tables. To comply with the expected operation these tables are typically realized by ordinary memory blocks and incorporates some algorithm to make the
lookup fast. In this work a table structure is realized with the use of Content
Addressable Memory (CAM) modules for the lookup process and will be evaluated, first of all to find out if a CAM actually can be used for the purpose and
secondly to find out, if it can support a network bandwidth of 2 Gbps.
At first the reader will be introduced to the fundamentals of the NAPT in Chapter 2, whereafter the actual analysis and design of a NAPT core is carried out.
The analysis and design Chapter 3 is structured in an itemized way, where the
different demands are treated. Typically the structure is equal for each item,
starting with an introduction to the problem followed up by one or more design solutions and finally the subject of the item is discussed with pro and cons
and relevant security considerations. The implemented parts of the project are
presented in Chapter 4 and a functional test of the implemented part is carried
out in Chapter 5. Finally the achived results are presented in Chapter 6 and a
discussion of potential future work is made in Chapter 7. In the last chapter 8
a conclusion is given.
||Technical University of Denmark (DTU) : Kgs. Lyngby, Denmark
Creation date: 2009-06-10
Update date: 2010-08-25