Beta 1

Title Testing and analyzing methods for truncated binary multiplication
Author Winther, Andreas Thor
Supervisor Nannarelli, Alberto (System-on-Chip Hardware, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Bachelor thesis
Year 2009
Abstract Multiplication operations are frequently required in digital signal processing. To increase the speed with which these are done, parallel multipliers can be used. These however require a large area on the chip and consume much power. An important goal would therefore be to reduce the area requirements. The purpose of this project is to analyze several methods of performing truncated multiplication and to determine which method would be most efficient for unsigned numbers of 8, 16 or 32 bits. Truncated multiplication is a technique where only the most significant columns of the multiplication matrix are used and therefore area requirements can be reduced by up to 46.08 % for 32 bit inputs. This however leads to a rounding error and a reduction error which needs to be corrected by introducing a correction constant, and the goal of this project is to determine the point of balance for error vs. hardware savings. The scope of this project is to evaluate different well-known area reduction methods along with minimizing the error. The multiplier is implemented using VHDL (VHSIC Hardware Description Language, where VHSIC stands for Very High Speed Integrated Circuit) and simulated with ModelSim/Xilinx ISE in order to observe the hardware area reduction. It is also implemented and simulated using Matlab’s Simulink tool in order to evaluate the error.
Series IMM-B.Sc.-2009-10
Original PDF bac09_10.pdf (0.90 MB)
Admin Creation date: 2009-07-01    Update date: 2010-10-28    Source: dtu    ID: 246043    Original MXD