Beta 1


Title Design of an FPGA based MPEG post-processing unit for HDTV
Author Eerola, Markku
Supervisor Nannarelli, Alberto (Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2009
Abstract This master's thesis focuses on the design of an FPGA based MPEG-2 post-processing unit for HDTV. Large at panel televisions are getting more and more common. As the television screen sizes grow and the resolution used the content increase heavy compression is required in order to t the transmitted video into the bandwidth allowed by the existing infrastructure. Compression-caused degradation in image quality becomes the bigger a problem the larger the screens are. Therefore it is meaningful in HDTV applications to employ post-processing on the decoded video in order to improve image quality. In this thesis a post-processing unit for MPEG-2 coded video signal is designed, implemented in VHDL and synthesized for a Xilinx Spartan XC3SD3400A FPGA. The chosen method involves using a fast 2-D DCT algorithm to retrieve quantized DCT coefficients for MPEG-2 intra-picture macroblocks, estimating MPEG quantization scale QS values for each macroblock, and using the calculated QS values to control the output of a deringing filter. The designed lter is tested and its performance is studied with simulations. The chosen scheme works, and the amount of ringing artifacts is reduced thus improving the perceived image quality.
Imprint Technical University of Denmark (DTU) : Kgs. Lyngby, Denmark
Series IMM-M.Sc.-2009-58
Fulltext
Original PDF ep09_58_net.pdf (1.00 MB)
Admin Creation date: 2009-09-30    Update date: 2009-11-04    Source: dtu    ID: 250579    Original MXD