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Title Design of a FPGA based HDTV post-processor
Author Sannino, Daniele
Supervisor Nannarelli, Alberto (Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Forchhammer, Søren (Coding and Visual Communication, Department of Photonics Engineering, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2010
Abstract The objective of the project is to develop and implement on an FPGA board algorithms for MPEG analysis and noise reduction to be used in a real time high-definition digital television (HDTV) environment. This is the continuation of two previous works: one concerning the blocking artifact and the other concerning the ringing artifact, both based on standard methodologies defined in MPEG4 video standard. The algorithms are designed to eliminate or reduce the artifacts introduced by the MPEG coding/decoding by selectively filtering the noise without degrading the overall image quality. In this thesis a post-processing unit based on a deringing algorithm developed at DTU is designed, implemented in VHDL and synthesized for a Xilinx Spartan FPGA. The chosen method involves using a fast 2-D DCT algorithm to retrieve quantized DCT coefficients for MPEG-2 intra-picture macroblocks, estimating MPEG Quantization Scale (QS) values for each macroblock, and using the calculated QS values to control the output of a deringing filter, in conjunction with the other parameters. The performance of the implemented algorithm has been evaluated by objective (Peak Signal to Noise Ratio) and subjective (visual inspection) criteria.
Imprint Technical University of Denmark (DTU) : Kgs. Lyngby, Denmark
Series IMM-M.Sc.-2010-02
Original PDF ep10_02_rev.pdf (2.26 MB)
Admin Creation date: 2010-04-09    Update date: 2010-10-28    Source: dtu    ID: 259734    Original MXD