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Title Design of Hardware Accelerators on Reconfigurable Platforms
Author Juul, Marie
Supervisor Nannarelli, Alberto (Embedded Systems Engineering, Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2010
Abstract Signal processing is widely used in numerous applications ranging from image-guided surgery to real-time computer games. These applications use algorithms that are highly data-intensive and would benefit from hardware acceleration. The Fast Fourier Transform (FFT) has inherent parallelism that is exploited in the hardware acceleration implementation. The ability to reconfigure the hardware accelerator-platform during CPU-runtime is highly beneficial, since certain data can call for a particular algorithm. The hardware accelerator was implemented on a Virtex-5 LX330T FPGA on the Alpha Data PCI Mezzanine Card, which with its SDK makes it possible to configure the FPGA at CPU-runtime, and to communicate with the board from the CPU during FPGA-runtime. This includes transferring data to the on-board off-FPGA RAM banks. The thesis focuses on what impact the data transfer between CPU and FPGA has on the total performance of the hardware accelerator. Focus is also on the performance of the designed hardware accelerator compared to the performance of the 3 GHz CPU executing the binary32 floating point 256-point 2D-FFT. The hardware accelerator was synthesized to a clock frequency of 66,7 MHz for the FFT-application. The accelerator was found to be significantly faster than the 3GHz CPU.
Imprint Technical University of Denmark (DTU) : Kgs. Lyngby, Denmark
Series IMM-M.Sc.-2010-74
Fulltext
Original PDF ep10_74.pdf (0.90 MB)
Admin Creation date: 2010-09-27    Update date: 2010-09-27    Source: dtu    ID: 267284    Original MXD