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Title Design of a low-power platform for running an embedded operating system
Author Jørgensen, Nicolai Ascanius
Supervisor Madsen, Jan (Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2003
Abstract Two existing processor cores have been used as the foundation of a low-power platform for running the embedded operating system, TinyOS. The first core is a MIPS core written in SystemC. The processor was extended with a coprocessor for executing timer interrupts. The second core is an AVR core written originally in VHDL. The core was translated to SystemC and some entities were re-written. For verification, a hamming encoder program and a TinyOS application was executed on the platforms. The power consumption of the executions was measured using the Synopsys Power Compiler. For the MIPS core, a subsection of TinyOS was translated from AVR assembly to MIPS assembly. The MIPS platform was synthesized to an FPGA and verified. Both platforms were clock gated using the Synopsys Power Compiler. All RTL design is written with the SystemC HDL. Sammenfatning på dansk: To eksisterende processorer er anvendt som grundlag for en lav-effekt platform til afvikling af det indlejrede operativsystem, TinyOS. Den første processor er en MIPS processor skrevet i SystemC. Processoren blev udvidet med en coprocessor til afvikling af timer interrupts. Den anden processor er en AVR processor oprindeligt skrevet i VHDL. Processoren er oversat til SystemC og nogle entiteter er blevet omskrevet. Til verifikation, er et hamming kodning program og en TinyOS applikation blevet afviklet på begge platforme. Strømforbruget under afvikling er målt med Synopsys Power Compiler. Til afvikling af TinyOS på MIPS platformen, er en del af TinyOS blevet oversat fra AVR assembler til MIPS assembler. MIPS platformen er syntetiseret til en FPGA og verificeret. Begge platforme er clock gated med Synopsys Power Compiler. Alt RTL design er skrevet med SystemC som HDL.
Imprint Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU : DK-2800 Kgs. Lyngby, Denmark
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Admin Creation date: 2006-06-22    Update date: 2012-12-20    Source: dtu    ID: 58631    Original MXD