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Title Optimal algorithms for GSM Viterbi modules
Author Wu, Kehuai (Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Supervisor Stassen, Flemming (Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark)
Institution Technical University of Denmark, DTU, DK-2800 Kgs. Lyngby, Denmark
Thesis level Master's thesis
Year 2003
Abstract A power/area optimum design of the 3rd-Generation Global System for Mobile communications(GSM 3G) unit's channel code decoder has been described. This decoder can perform the convolutional code decoding and the CRC check for a burst of transmitted data encoded by other GSM 3G units. The constraint length of the decoder varies between 5 and 7, the code rate varies from 2 to 6, and the received data are calibrated into 4 or 5-bit soft-decision bits. The power and area optimization is only considered at the algorithm and architecture level. The power/area effciency is measured from the gatelevel synthesis result. When the decoder is clocked at 100MHz and is given a 1.3V voltage supply, the measurement results show that the decoder's power consumption is typically less than 1.4mW. The decoder core consists of approximately 35.7 k gates (142.8 k transistors), which is equivalent to the area of 0:24mm 2 for the given 0.09 µm 5-metallayer CMOS technology.
Imprint Department of Informatics and Mathematical Modeling, Technical University of Denmark, DTU : DK-2800 Kgs. Lyngby, Denmark
Keywords Convolutional decoder; Viterbi algorithm; Low power; Low area; VLSI; GSM
Fulltext
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Admin Creation date: 2006-06-22    Update date: 2012-12-19    Source: dtu    ID: 58670    Original MXD