Beta 1


Title FPGA implementation of digital filters
Translated title FPGA implementation of digital filters
Author Christensen, Camilla Jin Egelund (Copenhagen University College of Engineering, IHK)
Supervisor Hjort, Robin Moll
Institution Ingeniørhøjskolen i København, IHK, DK-2750 Ballerup, Denmark
Thesis level Bachelor thesis
Education Diplomingeniør, Elektronik
Education !!Diplomingeniør, elektronik
Publication date 2012-06
Abstract This project focuses on two disciplines, within the FPGA and DSP area. It has been investigated how to design digital filters, in a FPGA, and a design of a compensation filter has been proposed, to combine the two disciplines into a relevant DSP application.
Via the developed system, it has been demonstrated how to design a system consisting of flexible system blocks, an architecture with a degree of freedom in the choice of input channels, number of clocks and different types of DSP blocks. Only an IIR filter has been designed, but the design/implementation of the filter block proved to be suitable for both IIR and FIR.
The resource usage has been estimated for three different DSP blocks: FIR, IIR and FFT, with the one thing in common: they should all be able to support enough throughputs for 128 input channels, while having enough computational power for their respective signal processing.
It is suggested that this work is used as an introduction to DSP design in FPGAs, because the project introduces some of the design challenges of digital filter design, in FPGAs, and it also described how to overcome some of the challenges.
Abstract This project focuses on two disciplines, within the FPGA and DSP area. It has been investigated how to design digital filters, in a FPGA, and a design of a compensation filter has been proposed, to combine the two disciplines into a relevant DSP application.
Via the developed system, it has been demonstrated how to design a system consisting of flexible system blocks, an architecture with a degree of freedom in the choice of input channels, number of clocks and different types of DSP blocks. Only an IIR filter has been designed, but the design/implementation of the filter block proved to be suitable for both IIR and FIR.
The resource usage has been estimated for three different DSP blocks: FIR, IIR and FFT, with the one thing in common: they should all be able to support enough throughputs for 128 input channels, while having enough computational power for their respective signal processing.
It is suggested that this work is used as an introduction to DSP design in FPGAs, because the project introduces some of the design challenges of digital filter design, in FPGAs, and it also described how to overcome some of the challenges.
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Admin Creation date: 2012-06-01    Update date: 2012-11-05    Source: ihk    ID: ihk-11329311    Original MXD